Nature

Low Power Design in CMOS and FinFET Logic Circuits

Low power design has become a cornerstone of modern integrated circuit development, driven by energy efficiency demands and the challenges of scaling in nanometre technologies. Innovations in ...
EDN

Power dissipation in portables: Design considerations using low-power CMOS ICs

When a CMOS circuit is in an idle state there is still some static power dissipation–a result of leakage current through nominally off transistors. Both nMOS and pMOS transistors used in CMOS logic ...
EDN

Design with (low) power while limiting leakage

Rapid development of portable systems like laptops, PDAs, digital wrist watches, implantable pacemakers and cell phones require low power consumption and high density ICs, and that leads to a surge of ...
Semiconductor Engineering

Forward Body Biasing in Bulk Cryo-CMOS With Negligible Leakage (TU Delft)

A new technical paper titled “Cryogenic-Aware Forward Body Biasing in Bulk CMOS” was published by researchers at QuTech, Tu Delft. “Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the ...
Electronic Design

ST to head European research to cut CMOS power consumption

Designers acknowledge that leakage currents are a primary problem for future generations of electronic circuits and systems. Designers acknowledge that leakage currents are a primary problem for ...
Electronic Design

Research Battles Leakage in CMOS Chips

STMicroelectronics recently announced it has taken a leadership role in a new European Integrated Project called CLEAN, which stands for Controlling Leakage power in NanoCMOS SoCs. Co-funded by the ...