The MSC Verification IP is compliant with 2005-01-0057 specification and verifies MSC Bus interfaces. It includes an extensive test suite covering most of the possible scenarios. It performs all ...

CEA-Leti, in its collaboration with Quobly, CEA-List and CEA-Irig, reported today it has developed a unique solution using FD-SOI CMOS technology that provides simultaneous microsecond readouts of ...

Atomic Rules TimeServo is a RTL IP core that serves the function of an FPGA’s System Timer or Clock. Although specifically designed to support the needs of line-rate independent packet timestamping, ...