EDN

4-bit ALU using VHDL

The project is a 4-bit ALU in VHDL with a total of 16 operations which includes various arithmetic, logical and data calculations performed by coding the ALU in VHDL code. The project is a 4-bit ALU ...
Design-Reuse

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...
EDN

FPGA design tool bypasses VHDL coding

CoDeveloper, a C language design tool for Altera Nios-based and Xilinx MicroBlaze-based programmable platforms, allows creation of a complete hardware/software application with no need to write VHDL ...
Electronic Design

VHDL/Verilog Simulator Shows 300% Speed Improvement

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...
CU Boulder News & Events

ECEA 5361 Hardware Description Languages for FPGA Design

This course will give you the foundation for using Hardware Description Languages, specifically VHDL and Verilog for Logic Design. You will learn the history of both VHDL and Verilog and how to use ...
Ars Technica

VHDL 4 bit multiplier

I am new to VHDL programming (although I've programmed in other languages like C++, java, etc.). I've been searching the web for help in writing a 4 bit multiplier (i.e. 0111 x 0110). I found sample ...
Electronic Design

New App From The Mathworks Generates HDL Code From System Models

[September 18, 2006] The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It ...